Sun Fire X4470 Server
 
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In this Document

Goal

Fix

Applies to:

Goal

The purpose of this document is to explain Hemisphere Mode - what does it do and how do you change Hemisphere Mode settings

Fix

Intel Xeon processor 7500 series-based platforms can configure Intel Xeon Processor 7500s to operate in Hemisphere Mode of operation where the processor's System Interface Controller (refer to Intel Xeon Processor 7500 Datasheet) will not access it's Global Coherence Engine (refer to Intel Xeon Processor 7500 Datasheet) thereby resulting in reduced memory latencies or increased performance.

This mode as shown in the diagram below or Figure 9-3 (of the Intel Xeon Processor 7500 Datasheet) requires identical memory configuration across the two memory controllers in terms of DIMMs and DRAM sizes. Since the two Hemisphere agents need to maintain the same memory configuration, a failing DIMM in one Hemisphere could result in software removing two lock-stepped DIMMs as well from the other
Hemisphere.





Hemisphere mode of operation has requirements with respect to memory mirroring and memory migration. Hemisphere mode allows memory migration between two directly connected sockets (inter socket migration), but both hemispheres must be migrated together.

Hemisphere mode can decrease memory latency by 7%, depending on workload. The effect of hemisphere Mode is more subtle in comparison to interleaving. If the system is in hemisphere mode, the latency of individual memory access improves slightly. The mode is possible if the following is true for each processor: the memory configuration is identical for both controllers.  This is an intensification of the previously required identical capacity in both controllers for 2-way interleaving. Hemisphere mode simplifies the processes for memory coherency: a check has to be made for every memory access as to whether the valid version of the block is in the DIMM or in the cache of another processor. And hemisphere mode reduces the number of agents involved by splitting the address space into an upper and lower hemisphere, which is equivalent to the first and second memory controller per processor.

Unequal DIMM capacity on the processors (Eg: P0/MR0 and P0/MR1) prevents hemisphere mode. Equal capacity on processors (Eg: P0/MR0 and P0/MR1) allows Hemisphere mode.  Hemisphere mode is enabled for each processor when the even and odd memory risers have the same total capacity of DRAM. 
During POST, BIOS notices it can split (interleave) the system memory between all even risers and all odd ones.  This is a system-wide mode (all processors enable the mode or not) and will be foiled by a DIMM fault on any memory riser.

If there is a "Hemispherical violation" on a 6 or 8 socket system, as could be the case on a Sun Fire X4800 if the DIMMs on opposite branches do not match in size, the BIOS will map them out and send a

WARN_USER_RANK_DISABLE

IPMI OEM message for each and send a

WARN_HEMISPHERE_SIZE_MISMATCH

OEM message as well.  This will inform the ILOM that the reason for the DIMMs being mapped out is because of a size mismatch and not a placement problem. The ILOM will then display that information to the user.

The Sun Fire X4470, in contrast, will operate in 4 sockets hemisphere with 2 IOHs  mode as default.  For 2 or 4 socket systems, hemisphere mode is preferred but can  be disabled. It is enabled by default and should contribute to better performance.

For 2 or 4 socket systems, hemisphere mode can be disabled by changing the following
setting in the BIOS.

BIOS Setup Utility: RC Settings, Integrated Memory Controller Configuration, hidden option (F4 key), "Hemisphere Mode".

Also refer to the following knowledge articles in MOS for memory faults where it is recommended that the DIMMs be populated in a manner where Hemisphere mode violations don't result.

SPX86-8001-U5 - Memory Uncorrectable ECC Fault (Doc ID 1021433.1)
SPX86-8001-NJ - Memory DIMM Population Rules Violated (Doc ID 1021425.1)
SPX86-8002-6R - Excessive Memory ECC correctable errors have occurred. (Doc ID 1174533.1)
SPX86-8001-JR - Memory DIMM Incompatible (Doc ID 1021408.1)
SPX86-8002-K2 - Memory branch-wide test failed. (Doc ID 1170023.1)
SPX86-8001-XH - Memory Not Present On Branch (Doc ID 1156943.1)
SPX86-8002-JJ - Memory Branch lane failover (Doc ID 1170003.1)
SPX86-8001-GY - Memory DIMM of Unknown Type (Doc ID 1021404.1)
SPX86-8001-YD - Memory located on a branch was not successfully initialized (Doc ID 1167453.1)

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