===============================================================================
RELEASE NOTES FOR V-SYSTEM VHDL/Verilog Version 4.4g
(14 November 1995)

(release notes for 4.4a, 4.4c, 4.4d, 4.4e and 4.4f follow)

CHANGES:
========

o Fixed memory leak in force/unforce commands
o Modified textio-read to deallocate lines after emptying them
o Fixed bug in memory management that occasionally caused crashes.
o Fixed Verilog index into net's on X or out-of-range indexes.
o Fixed Verilog $readmem to properly parse certain comments.
o Fixed Verilog `ifdef bug.

===============================================================================
RELEASE NOTES FOR V-SYSTEM VHDL/Verilog Version 4.4f
(3 November 1995)

(release notes for 4.4a, 4.4c, 4.4d and 4.4e follow)

CHANGES:
========

o Fixed 3 problems in VITAL 95 (VITAL 3.0) support.

===============================================================================
RELEASE NOTES FOR V-SYSTEM VHDL/Verilog Version 4.4e
(30 October 1995)

(release notes for 4.4a, 4.4c and 4.4d follow)

CHANGES:
========

o Fixed a problem with VITAL2.2b that had been introduced in release 4.4d.

o Fixed a problem with the structure window when different font sizes are
  used.

o Fixed a potential crash when dragging signal names in the wave window.

NOTES:
======

o Please be aware of the following limitation on length of Tcl commands:
  A Tcl command cannot exceed 4096 bytes in length -- if it does, the
  simulation will likely crash without explanation. By Tcl command, this 
  includes procedure call declarations, and the sum of all clauses of an
  if/then/else statement. Keep things short and you will be ok.

  This is a limitation of our interface to Tcl, and not a limitation of Tcl
  itself. The problem will be fixed in release 5.0. We apologize if it has
  caused you any inconvenience.

===============================================================================
RELEASE NOTES FOR V-SYSTEM VHDL/Verilog Version 4.4d
(18 October 1995)

(release notes for 4.4a and 4.4c follow)

NEW FEATURES
============

	1) VITAL 95 Support. This is the default. To run VITAL 2.2b, use the
	   "-vital2.2b" option for both VCOM and VSIM.

CHANGES:
========

o Changed -view mode to disable the source, process, variable and
  dataflow windows. Print a message to the transcript indicating they
  are disabled in this mode.

o Allow environment variables to be in a FILE variable being opened
  in VHDL. Note that ~ is not expanded, only environment variables.


	entity test is end;
	use std.textio.all;
	architecture only of test is
	begin
		process
			FILE  in_file  :  text is in "$ENV_VAR_NAME";
		begin
			wait;
		end process;
	end;

o Fixed bug so 'last_value works for a vhdl signal whose input port
  is coming from a Verilog modules

===============================================================================
RELEASE NOTES FOR V-SYSTEM VHDL/Verilog Version 4.4c
(28 September 1995)


NEW FEATURES (over 4.4a):
=========================

    1) Accelerated IEEE numeric_std and numeric_bit arithmetic packages. 
       (beta version)
    2) Keyboard shortcuts for the wave window
    3) New simulator control variables
    4) Additional simulator commands
    5) Verilog PATHPULSE$ supported
    6) Verilog $setuphold support for negative constraints


CHANGES:
========

o The pre-compiled ieee library contains the accelerated IEEE packages.
  Use the ieeepure library if you prefer an ieee library that contains only
  the std_logic_1164 package.

o The VSIM waveform window now properly handles waveforms of variable height. 

o VSIM analog waveform interpolation is changed to give the user the option
  of rectilinear or diagonal lines (see below).

o Fixed a large memory leak occuring on restart, and a memory leak occuring
  when the user allocates large blocks.

o Fixed a bug in the VSIM Force command that may eventually cause the 
  simulation to crash.

o Bugs fixed in the Verilog PLA system tasks.

o Bug fixed in Verilog conditional operator when the condition is unknown.

o Bug fixed in Verilog concatenations of registers sized by parameters.

o Bug fixed in Verilog $display of registers having embedded NULL characters.



DETAILS OF NEW FEATURES:

Accelerated IEEE numeric_std and numeric_bit arithmetic packages. 
====================================================================

We are including a preliminary fully accelerated version of the 
recently balloted IEEE synthesis arithmetic packages. If you use the 
ieee library supplied with the 4.4c release, you will automatically 
get the acceleration. If you have problems with this, invoking vcom
with "-noaccel numeric_std" will turn off acceleration of the numeric_std
package.

The numeric_std package contains the following functions:

  function "abs" (ARG: SIGNED) return SIGNED;
  function "-" (ARG: SIGNED) return SIGNED;
  function "+" (L, R: UNSIGNED) return UNSIGNED;
  function "+" (L, R: SIGNED) return SIGNED;
  function "+" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
  function "+" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
  function "+" (L: INTEGER; R: SIGNED) return SIGNED;
  function "+" (L: SIGNED; R: INTEGER) return SIGNED;
  function "-" (L, R: UNSIGNED) return UNSIGNED;
  function "-" (L, R: SIGNED) return SIGNED;
  function "-" (L: UNSIGNED;R: NATURAL) return UNSIGNED;
  function "-" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
  function "-" (L: SIGNED; R: INTEGER) return SIGNED;
  function "-" (L: INTEGER; R: SIGNED) return SIGNED;
  function "*" (L, R: UNSIGNED) return UNSIGNED;
  function "*" (L, R: SIGNED) return SIGNED;
  function "*" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
  function "*" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
  function "*" (L: SIGNED; R: INTEGER) return SIGNED;
  function "*" (L: INTEGER; R: SIGNED) return SIGNED;
  function "/" (L, R: UNSIGNED) return UNSIGNED;
  function "/" (L, R: SIGNED) return SIGNED;
  function "/" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
  function "/" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
  function "/" (L: SIGNED; R: INTEGER) return SIGNED;
  function "/" (L: INTEGER; R: SIGNED) return SIGNED;
  function "rem" (L, R: UNSIGNED) return UNSIGNED;
  function "rem" (L, R: SIGNED) return SIGNED;
  function "rem" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
  function "rem" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
  function "rem" (L: SIGNED; R: INTEGER) return SIGNED;
  function "rem" (L: INTEGER; R: SIGNED) return SIGNED;
  function "mod" (L, R: UNSIGNED) return UNSIGNED;
  function "mod" (L, R: SIGNED) return SIGNED;
  function "mod" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
  function "mod" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
  function "mod" (L: SIGNED; R: INTEGER) return SIGNED;
  function "mod" (L: INTEGER; R: SIGNED) return SIGNED;
  function ">" (L, R: UNSIGNED) return BOOLEAN;
  function ">" (L, R: SIGNED) return BOOLEAN;
  function ">" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
  function ">" (L: INTEGER; R: SIGNED) return BOOLEAN;
  function ">" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
  function ">" (L: SIGNED; R: INTEGER) return BOOLEAN;
  function "<" (L, R: UNSIGNED) return BOOLEAN;
  function "<" (L, R: SIGNED) return BOOLEAN;
  function "<" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
  function "<" (L: INTEGER; R: SIGNED) return BOOLEAN;
  function "<" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
  function "<" (L: SIGNED; R: INTEGER) return BOOLEAN;
  function "<=" (L, R: UNSIGNED) return BOOLEAN;
  function "<=" (L, R: SIGNED) return BOOLEAN;
  function "<=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
  function "<=" (L: INTEGER; R: SIGNED) return BOOLEAN;
  function "<=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
  function "<=" (L: SIGNED; R: INTEGER) return BOOLEAN;
  function ">=" (L, R: UNSIGNED) return BOOLEAN;
  function ">=" (L, R: SIGNED) return BOOLEAN;
  function ">=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
  function ">=" (L: INTEGER; R: SIGNED) return BOOLEAN;
  function ">=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
  function ">=" (L: SIGNED; R: INTEGER) return BOOLEAN;
  function "=" (L, R: UNSIGNED) return BOOLEAN;
  function "=" (L, R: SIGNED) return BOOLEAN;
  function "=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
  function "=" (L: INTEGER; R: SIGNED) return BOOLEAN;
  function "=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
  function "=" (L: SIGNED; R: INTEGER) return BOOLEAN;
  function "/=" (L, R: UNSIGNED) return BOOLEAN;
  function "/=" (L, R: SIGNED) return BOOLEAN;
  function "/=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
  function "/=" (L: INTEGER; R: SIGNED) return BOOLEAN;
  function "/=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
  function "/=" (L: SIGNED; R: INTEGER) return BOOLEAN;
  function SHIFT_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
  function SHIFT_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
  function SHIFT_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
  function SHIFT_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
  function ROTATE_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
  function ROTATE_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
  function ROTATE_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
  function ROTATE_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
  function "sll" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED;
  function "sll" (ARG: SIGNED; COUNT: INTEGER) return SIGNED;
  function "srl" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED;
  function "srl" (ARG: SIGNED; COUNT: INTEGER) return SIGNED;
  function "rol" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED;
  function "rol" (ARG: SIGNED; COUNT: INTEGER) return SIGNED;
  function "ror" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED;
  function "ror" (ARG: SIGNED; COUNT: INTEGER) return SIGNED;
  function RESIZE (ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED;
  function RESIZE (ARG: UNSIGNED; NEW_SIZE: NATURAL) return UNSIGNED;
  function TO_INTEGER (ARG: UNSIGNED) return NATURAL;
  function TO_INTEGER (ARG: SIGNED) return INTEGER;
  function TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED;
  function TO_SIGNED (ARG: INTEGER; SIZE: NATURAL) return SIGNED;
  function "not" (L: UNSIGNED) return UNSIGNED;
  function "and" (L, R: UNSIGNED) return UNSIGNED;
  function "or" (L, R: UNSIGNED) return UNSIGNED;
  function "nand" (L, R: UNSIGNED) return UNSIGNED;
  function "nor" (L, R: UNSIGNED) return UNSIGNED;
  function "xor" (L, R: UNSIGNED) return UNSIGNED;
  function "xnor" (L, R: UNSIGNED) return UNSIGNED;
  function "not" (L: SIGNED) return SIGNED;
  function "and" (L, R: SIGNED) return SIGNED;
  function "or" (L, R: SIGNED) return SIGNED;
  function "nand" (L, R: SIGNED) return SIGNED;
  function "nor" (L, R: SIGNED) return SIGNED;
  function "xor" (L, R: SIGNED) return SIGNED;
  function "xnor" (L, R: SIGNED) return SIGNED;
  function STD_MATCH (L, R: STD_ULOGIC) return BOOLEAN;
  function STD_MATCH (L, R: UNSIGNED) return BOOLEAN;
  function STD_MATCH (L, R: SIGNED) return BOOLEAN;
  function STD_MATCH (L, R: STD_LOGIC_VECTOR) return BOOLEAN;
  function STD_MATCH (L, R: STD_ULOGIC_VECTOR) return BOOLEAN;
  function TO_01 (S: UNSIGNED; XMAP: STD_LOGIC := '0') return UNSIGNED;
  function TO_01 (S: SIGNED; XMAP: STD_LOGIC := '0') return SIGNED;

As in release 4.4a, the accelerated Synopsys synthesis arithmetic packages 
are also automatically included in the supplied ieee library. These are
std_logic_arith, std_logic_unsigned, and std_logic_signed.

If you prefer a stripped down ieee library, change your mapping to point
to <install-dir>/ieee_pure.


Keyboard shortcuts for the wave window
======================================

Hitting the following keys with the mouse cursor within the wave window
will cause the indicated actions:

        Key                        Action
    =============== ============================================

       <tab>          .wave right (searches forward to the next transition on the
                                   selected signal)

     <shift-tab>      .wave left  (searches backward to the previous transition on the
                                   selected signal)

       i I or +       zoom in

       o O or -       zoom out

       f or F         zoom full

       l or L         zoom last

       r of R         zoom range


New simulator control variables:
================================

The following Tcl simulator control variables have been added to VSIM.
(These properties previously could only be changed manually using popup menus
or in some cases via the vsystem.ini file.)

    Variable name        Value range                    Purpose
===================== ============== ======================================

    SignalViewMask        0-15        Determines what kinds of signals the
                                      signals window displays. The value is
                                      a sum of the following:

                                        view inputs         1
                                        view outputs        2
                                        view inouts         4
                                        view internals      8

    WaveSignalNameWidth  pos int      Same as the Max Signal Name Width
                                      field of the WAVE->PROPS->DISPLAY
                                      popup.

    WaveSnapDistance     pos int      Same as the Snap Distance field of the
                                      WAVE->PROPS->DISPLAY popup.

    DefaultRadix       0,2,8,10,16    Same as the Default Radix field of the
                                      MAIN->PROPS simulation category popup.

    ListDefaultShortName   0,1        Same as the Label field of the 
                                      LIST->PROPS->DEFAULTS popup. A '1'
                                      corresponds to Short Name, and '0' to 
                                      Full Name.

    ListDefaultIsTrigger   0,1        Same as the Trigger filed of the
                                      LIST->PROPS->DEFAULTS popup. A '1'
                                      indicates that the default is for signals
                                      to trigger the list display.

    ListCollapseDeltas     0,1        Same as the Deltas field of the
                                      LIST->PROPS->TRIGGERS popup. A '1'
                                      indicates that deltas will be collapsed.

    ListUseStrobe          0,1        Same as the Strobe button of the
                                      "Trigger on" field of the
                                      LIST->PROPS->TRIGGERS popup. A '1'
                                      indicates that strobe will be active.

    ListUseSignalTriggers  0,1        Same as the Signals button of the
                                      "Trigger on" field of the
                                      LIST->PROPS->TRIGGERS popup. A '1'
                                      indicates that signal triggering will be 
                                      active.

    ListStrobePeriod     pos int      Same as the "Strobe period" field of the
                                      LIST->PROPS->TRIGGERS popup. 

    ListStrobeStart      pos int      Same as the "First strobe at" field of the
                                      LIST->PROPS->TRIGGERS popup. 

    DelayFileOpen           0,1       Same as the DelayFileOpen field of the
                                      vsystem.ini file.

    InterpolateAnalog       0,1       If true, draws diagonal lines between 
                                      successive analog values, otherwise draws
                                      rectangularly. Default is 0.

    EnableXdefaultsWrite    0,1       If true, enables writing of the $HOME/.Xdefaults
                                      file when vsim colors are changed. Otherwise
                                      colors are changed in the resource database only.
                                      Default is 1.


Additional simulator commands:
==============================

The following new commands are available on the VSIM command line and
in macros. The "." is actually part of the command name.


    Command             Arguments                      Purpose
===================== ============== ======================================

.Wave Zoom Full          (none)       Same as the WAVE->ZOOM->FULL_SIZE menu pick

.Wave Zoom Range      f1 f2 [res]     Sets the waveform display to zoom from time f1
                                      to f2, where f1 and f2 are floating point
                                      numbers, and res is an optional VHDL time 
                                      resolution, such as ns. Behavior is the same
                                      as the WAVE->ZOOM->RANGE popup.
                                      Example:

                                      .w z r 1.500 1.750 ms
                                      .w z f

.Process   Get_position   <coord>          
.STructure Get_position   <coord>          
.Variables Get_position   <coord>          
.SIgnals   Get_position   <coord>          
.Main      Get_position   <coord>          
.SOurce    Get_position   <coord>          
.Dataflow  Get_position   <coord>          
.List      Get_position   <coord>          
.Wave      Get_position   <coord>          
                                      Returns an integer cooresponding to the
                                      window coordinate requested. <coord>
                                      can be x, y, width, height or icon. When
                                      icon is specified, a "1" is returned if
                                      the window is currently iconified, otherwise
                                      a "0" is returned. (To set window positions
                                      from the command line, see new options to the
                                      View command.)

.Wave Sig_prop  {<option>}  <name>    Changes one or more specified properties of
                                      signal <name>. <name> may be a wild card
                                      pattern.  These properties correspond
                                      to those than can be specified using the
                                      WAVE->PROP->SIGNAL popup. The options are:

                                            -Height   <number>
                                            -Color    <color>
                                            -Format   Analog, LIteral or LOgic
                                            -Offset   <number>
                                            -Scale    <float>
                                            -Radix    Symbolic, Bin, Oct, Dec or Hex

                                      For multiple-word color names, use double
                                      quotes or curly braces.
                                      The offset and scale options are only valid
                                      when format has been specified as analog.

.List Sig_prop  {<option>}  <name>    Changes one or more specified properties of
                                      signal <name>. <name> may be a wild card
                                      pattern. These properties correspond
                                      to those than can be specified using the
                                      LIST->PROP->SIGNAL popup. The options are:

                                            -Label    <label>
                                            -Width    <number>
                                            -Radix    Symbolic, Bin, Oct, Dec or Hex
                                            -Trigger  0 or 1

                                      Setting trigger to 1 will enable the list
                                      window to be triggered by changes on this
                                      signal.

.SOurce line             <number>     Scrolls the source window to display line
                                      number <number> on currently displayed file.

.SOurce file             <name>       Changes the file displayed by the source
                                      window to <name>.

.Process   Color    <field> <color>    
.STructure Color    <field> <color>    
.Variables Color    <field> <color>    
.SIgnals   Color    <field> <color>    
.Wave      Color    <field> <color>    
                                      Sets the color of the specified window field 
                                      to the specified X-Window color name <color>. 

                                      Allowed fields for the wave window are:
                                      BAckground, GRid, TIme, CUrsor, DElta, TExt,
                                      VEctor, LX, L0, L1, LZ,
                                      which affect the waveform display pane, and:
                                      NBackground, NText, NOutline, NFill, which
                                      affect the wave signal name pane.

                                      Allowed fields for the other windows are:
                                      Background, Text, Outline and Fill.

.Main Clear                           Clears the transcript window, deleting anything
                                      previously recorded there, and clears the
                                      transcript file, if any. Works only under
                                      Motif.



===============================================================================
RELEASE NOTES FOR V-SYSTEM VHDL/Verilog Version 4.4a
(11 August 1995)


New Features:
=============

o Verilog and mixed VHDL/Verilog designs.

o Logic Modeling hardware modeler.

o Accelerated Synopsys packages: std_logic_arith, std_logic_signed,
  and std_logic_unsigned.


Changes:
========

o Libraries compiled with earlier versions of V-System must be recompiled
  to run with this release of V-System.

o Log files (vsim.wav) created with earlier versions of V-System cannot
  be read with the -view option of this release of VSIM.

o The VITAL packages are pre-compiled into the vital library in the
  installation directory. The new vsystem.ini file contains a default
  library mapping to the pre-compiled vital library.

o The pre-compiled ieee library contains the accelerated Synopsys packages.
  Use the ieeepure library if you prefer an ieee library that contains only
  the std_logic_1164 package.

o Revised User's Manual describes new Verilog features and how to mix
  VHDL and Verilog.

o The new "docs" subdirectory in the installation directory contains
  on-line documentation such as technical notes and information on
  the new Verilog features.

o Object names in VSIM commands are case sensitive. Use lowercase names
  for VHDL identifiers in VSIM commands. For example, use "/top/siga"
  rather than "/TOP/SIGA". You may disable case sensitivity by setting
  the TCL variable ObjectsCaseSensitive to 0.

o Design unit names on the VSIM command line are case sensitive. Use
  lowercase names on the VSIM command line. For example, "vsim top"
  rather than "vsim TOP". The ObjectsCaseSensitive variable does not
  affect the command line.

o SDF mapping for HOLD can be changed by invoking VSIM with -sdfholdv3.
  The default mapping is thold_<clock>_<data>. Use -sdfholdv3 to change
  the mapping to thold_<data>_<clock>. The need for the switch arises
  from ambiguities in the VITAL 2.2b specification and the clarification
  on the HOLD mapping in the VITAL 3.0 specification.


Verilog:
========

The Verilog features of V-System consist of a Verilog compiler (VLOG)
and a dual-language simulator (VSIM). A "vlog" authorization code
is required to run the compiler, and a "vsim-vlog" authorization code
is required to simulate a Verilog design.

The new V-System User's Manual describes how to use the Verilog features.
In addition, the following on-line documentation is available in
"<install_dir>/docs/verilog":

    guide      - how to use the Verilog features.
    mixedhdl   - how to mix VHDL and Verilog.
    directives - list of supported compiler directives.
    pli        - list of supported PLI routines.
    systasks   - list of supported system tasks and functions.

Also, an example mixed VHDL/Verilog design is provided in
"<install_dir>/examples/mixedHDL".

The Verilog implementation is based on the draft IEEE 1364 specification.
This specification is derived from the OVI 2.0 LRM, the OVI 1.0 PLI
Manual, and the OVI 2.0 PLI Manual. These reference materials are not
provided with V-System, it is left to the user to obtain the Verilog
reference manuals.

The 4.4a release of V-System does not fully implement the IEEE 1364
specification. Mainly, the exceptions are PLI Access routines and SDF
annotation. The next several releases will move towards a complete
implementation by the end of the year. First priority will be
completion of the PLI Access routines and SDF annotation. The following
is a list of unsupported features, system tasks, and PLI routines:

Unsupported features:
---------------------

    Value Change Dump file
    SDF annotation (the VITAL -sdf options do not apply to Verilog designs)
    Array of instances
    PATHPULSE$

Unsupported system tasks:
-------------------------

    $dist_chi_square
    $dist_t
    $dumpall
    $dumpfile
    $dumpflush
    $dumplimit
    $dumpoff
    $dumpon
    $dumpvars

Unsupported PLI callback reasons:
---------------------------------

    reason_paramdrc
    reason_force
    reason_release
    reason_disable
    reason_interactive

Unsupported PLI routines:
-------------------------

    acc_append_delays
    acc_append_pulsere
    acc_collect
    acc_compare_handles
    acc_count
    acc_fetch_argc
    acc_fetch_argv
    acc_fetch_attribute
    acc_fetch_attribute_int
    acc_fetch_attribute_str
    acc_fetch_delay_mode
    acc_fetch_delays
    acc_fetch_direction
    acc_fetch_edge
    acc_fetch_index
    acc_fetch_paramtype
    acc_fetch_paramval
    acc_fetch_polarity
    acc_fetch_pulsere
    acc_fetch_value
    acc_free
    acc_handle_condition
    acc_handle_conn
    acc_handle_datapath
    acc_handle_hiconn
    acc_handle_loconn
    acc_handle_modpath
    acc_handle_notifier
    acc_handle_path
    acc_handle_pathin
    acc_handle_pathout
    acc_handle_port
    acc_handle_simulated_net
    acc_handle_tchk
    acc_handle_tchkarg1
    acc_handle_tchkarg2
    acc_handle_terminal
    acc_handle_tfarg
    acc_handle_itfarg
    acc_next
    acc_next_bit
    acc_next_cell
    acc_next_cell_load
    acc_next_driver
    acc_next_hiconn
    acc_next_input
    acc_next_load
    acc_next_loconn
    acc_next_modpath
    acc_next_net
    acc_next_output
    acc_next_parameter
    acc_next_port
    acc_next_portout
    acc_next_primitive
    acc_next_specparam
    acc_next_tchk
    acc_next_terminal
    acc_object_in_typelist
    acc_object_of_type
    acc_release_object
    acc_replace_delays
    acc_replace_pulsere
    acc_set_interactive_scope
    acc_set_pulsere
    acc_set_value
    acc_vcl_add
    acc_vcl_delete
    tf_strdelputp
    tf_istrdelputp
    tf_strlongdelputp
    tf_istrlongdelputp
    tf_strrealdelputp
    tf_istrrealdelputp
    vpi_chk_error
    vpi_compare_objects
    vpi_free_object
    vpi_get
    vpi_get_cb_info
    vpi_get_delays
    vpi_get_str
    vpi_get_systf_info
    vpi_get_time
    vpi_get_value
    vpi_get_vlog_info
    vpi_handle
    vpi_handle_by_index
    vpi_handle_by_name
    vpi_handle_multi
    vpi_iterate
    vpi_mcd_close
    vpi_mcd_name
    vpi_mcd_open
    vpi_mcd_printf
    vpi_printf
    vpi_put_delays
    vpi_put_value
    vpi_register_cb
    vpi_register_systf
    vpi_remove_cb
    vpi_scan


Logic Modeling Hardware Modeler
===============================

Before you can instantiate a hardware model in your design, you
must first create a VHDL entity with the HM_ENTITY tool.
HM_ENTITY takes a shell software filename as its only argument
and writes a VHDL entity and foreign architecture to stdout.
The Logic Modeling environment variables LM_DIR and LM_LIB
must be set before running HM_ENTITY. Documentation on these
environment variables, shell software files, and the hardware
modeler are supplied by Logic Modeling.

The following VSIM commands are available for hardware models:

    lm_vectors on|off <instance_name> [<filename>]
    lm_measure_timing on|off <instance_name> [<filename>]
    lm_timing_checks on|off [<instance_name>]
    lm_loop_patterns on|off <instance_name>
    lm_unknowns on|off [<instance_name>]

These commands are described in the LMC documentation.


Logic Modeling SmartModels and Verilog
======================================

The Logic Modeling SWIFT-based SmartModel library is supported by
by V-System. Details on how to use the SmartModel library are
provided in the User's Manual.

Before you can instantiate a SmartModel in your design, you must
first create a VHDL entity with the SM_ENTITY tool. Currently,
you must create a VHDL entity even if you are instantiating the
SmartModel from a Verilog design. You can then instantiate the
entity from Verilog as though it were a Verilog module. A
limitation of this approach is that the SmartModel attributes
must be set through module instance parameters, but not defparam
statements.

If you are currently using the SmartModel library with Cadence
Verilog, you should be aware of the following:

    - The Cadence Verilog version of the SmartModel library is not
      SWIFT-based, and you must obtain the SWIFT library from Logic
      Modeling.

    - The interface to Cadence SmartModels is different than the
      interface to SWIFT SmartModels. In general, the port interfaces
      are the same, but the SmartModel attribute names are
      different. For example, the TimingVersion attribute in SWIFT
      SmartModels is named COMP in Cadence SmartModels.


Foreign Language Interface
==========================

The foreign language interface routines (mti_*) are designed to work
with VHDL designs and VHDL objects. However, these routines can also
be used on Verilog instances in a mixed VHDL/Verilog design. In
addition, the routines for traversing the design hierarchy also
recognize Verilog instances.

The following routines operate on Verilog instances as follows:

    mti_GetTopRegion - Gets the first top-level module. Use
        mti_NextRegion to get additional top-level modules.

    mti_GetPrimaryName - Gets the module name.

    mti_GetSecondaryName - Returns NULL for Verilog modules.

The following routines operate on Verilog instances in the same
manner that they operate on VHDL instances:

    mti_CreateRegion
    mti_FindRegion
    mti_FirstLowerRegion
    mti_GetCurrentRegion
    mti_GetLibraryName
    mti_GetRegionFullName
    mti_GetRegionName
    mti_GetRegionSourceName
    mti_HigherRegion
    mti_NextRegion

All other routines only operate on VHDL instances and objects.
Specifically, the routines that operate on VHDL signals and drivers
cannot be used on Verilog nets and drivers. For example, a call to
mti_FirstSignal on a Verilog region always returns NULL. You must
use the PLI routines to operate on Verilog objects. In addition,
the following routines exclude Verilog nets and ports in the case
of connections between VHDL and Verilog:

    mti_GetDrivingPorts
    mti_GetReadingPorts
    mti_GetParentSignal

