function [ret,x0,str,ts,xts]=extrflip(t,x,u,flag);
%EXTRFLIP	is the M-file description of the SIMULINK system named EXTRFLIP.
%	The block-diagram can be displayed by typing: EXTRFLIP.
%
%	SYS=EXTRFLIP(T,X,U,FLAG) returns depending on FLAG certain
%	system values given time point, T, current state vector, X,
%	and input vector, U.
%	FLAG is used to indicate the type of output to be returned in SYS.
%
%	Setting FLAG=1 causes EXTRFLIP to return state derivatives, FLAG=2
%	discrete states, FLAG=3 system outputs and FLAG=4 next sample
%	time. For more information and other options see SFUNC.
%
%	Calling EXTRFLIP with a FLAG of zero:
%	[SIZES]=EXTRFLIP([],[],[],0),  returns a vector, SIZES, which
%	contains the sizes of the state vector and other parameters.
%		SIZES(1) number of states
%		SIZES(2) number of discrete states
%		SIZES(3) number of outputs
%		SIZES(4) number of inputs
%		SIZES(5) number of roots (currently unsupported)
%		SIZES(6) direct feedthrough flag
%		SIZES(7) number of sample times
%
%	For the definition of other parameters in SIZES, see SFUNC.
%	See also, TRIM, LINMOD, LINSIM, EULER, RK23, RK45, ADAMS, GEAR.

% Note: This M-file is only used for saving graphical information;
%       after the model is loaded into memory an internal model
%       representation is used.

% the system will take on the name of this mfile:
sys = mfilename;
new_system(sys)
simver(1.3)
if (0 == (nargin + nargout))
     set_param(sys,'Location',[287,179,555,556])
     open_system(sys)
end;
set_param(sys,'algorithm',     'RK-45')
set_param(sys,'Start time',    '0.0')
set_param(sys,'Stop time',     '3')
set_param(sys,'Min step size', '0.001')
set_param(sys,'Max step size', '.01')
set_param(sys,'Relative error','1e-3')
set_param(sys,'Return vars',   '')


%     Subsystem  'D flip-flop'.

new_system([sys,'/','D flip-flop'])
set_param([sys,'/','D flip-flop'],'Location',[133,229,683,418])

add_block('built-in/Transport Delay',[sys,'/','D flip-flop/Transport Delay'])
set_param([sys,'/','D flip-flop/Transport Delay'],...
		'orientation',2,...
		'Initial Input','ini',...
		'position',[395,115,440,145])

add_block('built-in/Inport',[sys,'/','D flip-flop/in_1'])
set_param([sys,'/','D flip-flop/in_1'],...
		'Port','2',...
		'position',[20,50,40,70])


%     Subsystem  'D flip-flop/AND'.

new_system([sys,'/','D flip-flop/AND'])
set_param([sys,'/','D flip-flop/AND'],'Location',[59,237,323,377])

add_block('built-in/Outport',[sys,'/','D flip-flop/AND/out_1'])
set_param([sys,'/','D flip-flop/AND/out_1'],...
		'position',[215,65,235,85])

add_block('built-in/Combinatorial Logic',[sys,'/','D flip-flop/AND/AND'])
set_param([sys,'/','D flip-flop/AND/AND'],...
		'Truth Table','[0;0;0;1]',...
		'position',[130,55,185,95])

add_block('built-in/Mux',[sys,'/','D flip-flop/AND/Mux'])
set_param([sys,'/','D flip-flop/AND/Mux'],...
		'inputs','2',...
		'position',[65,55,95,90])

add_block('built-in/Inport',[sys,'/','D flip-flop/AND/in_1'])
set_param([sys,'/','D flip-flop/AND/in_1'],...
		'position',[15,55,35,75])

add_block('built-in/Inport',[sys,'/','D flip-flop/AND/in_2'])
set_param([sys,'/','D flip-flop/AND/in_2'],...
		'Port','2',...
		'position',[15,70,35,90])
add_line([sys,'/','D flip-flop/AND'],[100,75;125,75])
add_line([sys,'/','D flip-flop/AND'],[40,65;60,65])
add_line([sys,'/','D flip-flop/AND'],[40,80;60,80])
add_line([sys,'/','D flip-flop/AND'],[190,75;210,75])
set_param([sys,'/','D flip-flop/AND'],...
		'Mask Display','AND',...
		'Mask Type','AND',...
		'Mask Dialogue','AND Gate',...
		'Mask Help','Calculates the logical AND of the two inputs.')


%     Finished composite block 'D flip-flop/AND'.

set_param([sys,'/','D flip-flop/AND'],...
		'position',[215,39,250,66])

add_block('built-in/Transport Delay',[sys,'/','D flip-flop/Transport Delay1'])
set_param([sys,'/','D flip-flop/Transport Delay1'],...
		'Initial Input','1',...
		'position',[80,10,130,40])

add_block('built-in/Inport',[sys,'/','D flip-flop/in_2'])
set_param([sys,'/','D flip-flop/in_2'],...
		'position',[160,60,180,80])

add_block('built-in/Mux',[sys,'/','D flip-flop/Mux1'])
set_param([sys,'/','D flip-flop/Mux1'],...
		'inputs','3',...
		'position',[275,47,305,93])

add_block('built-in/Demux',[sys,'/','D flip-flop/Demux'])
set_param([sys,'/','D flip-flop/Demux'],...
		'outputs','2',...
		'position',[405,50,445,85])

add_block('built-in/Combinatorial Logic',[sys,'/','D flip-flop/Logic'])
set_param([sys,'/','D flip-flop/Logic'],...
		'Truth Table','[0 1;1 0;0 1;1 0;0 1;0 1;1 0;1 0]',...
		'position',[325,50,380,90])

add_block('built-in/Outport',[sys,'/','D flip-flop/out_1'])
set_param([sys,'/','D flip-flop/out_1'],...
		'position',[485,50,505,70])

add_block('built-in/Outport',[sys,'/','D flip-flop/out_2'])
set_param([sys,'/','D flip-flop/out_2'],...
		'Port','2',...
		'position',[515,65,535,85])

add_block('built-in/Fcn',[sys,'/','D flip-flop/Fcn'])
set_param([sys,'/','D flip-flop/Fcn'],...
		'orientation',2,...
		'Expr','u[1]>.2',...
		'position',[280,118,325,142])

add_block('built-in/Fcn',[sys,'/','D flip-flop/Fcn1'])
set_param([sys,'/','D flip-flop/Fcn1'],...
		'Expr','u[1]<.2',...
		'position',[150,13,180,37])
add_line([sys,'/','D flip-flop'],[310,70;320,70])
add_line([sys,'/','D flip-flop'],[385,70;400,70])
add_line([sys,'/','D flip-flop'],[450,60;460,60;460,130;445,130])
add_line([sys,'/','D flip-flop'],[185,70;270,70])
add_line([sys,'/','D flip-flop'],[450,60;480,60])
add_line([sys,'/','D flip-flop'],[450,75;510,75])
add_line([sys,'/','D flip-flop'],[135,25;145,25])
add_line([sys,'/','D flip-flop'],[185,25;200,25;210,45])
add_line([sys,'/','D flip-flop'],[45,60;210,60])
add_line([sys,'/','D flip-flop'],[45,60;60,60;60,25;75,25])
add_line([sys,'/','D flip-flop'],[255,55;270,55])
add_line([sys,'/','D flip-flop'],[390,130;330,130])
add_line([sys,'/','D flip-flop'],[275,130;250,130;250,85;270,85])
set_param([sys,'/','D flip-flop'],...
		'Mask Display','D   1\n\n>   0',...
		'Mask Type','D flip-flop',...
		'Mask Dialogue','D flip-flop|Initial State for Output "1":',...
		'Mask Translate','ini=(@1~=0);')
set_param([sys,'/','D flip-flop'],...
		'Mask Help','While the clock signal is high, the output will be the same as the input signal.  The flip-flop then latches to the value of the input at the trailing edge of the clock pulse for the remainder of the clock cycle.')
set_param([sys,'/','D flip-flop'],...
		'Mask Entries','0\/')


%     Finished composite block 'D flip-flop'.

set_param([sys,'/','D flip-flop'],...
		'position',[170,31,205,84])


%     Subsystem  'JK flip-flop'.

new_system([sys,'/','JK flip-flop'])
set_param([sys,'/','JK flip-flop'],'Location',[446,189,1049,421])

add_block('built-in/Fcn',[sys,'/','JK flip-flop/Fcn1'])
set_param([sys,'/','JK flip-flop/Fcn1'],...
		'Expr','u[1]<.2',...
		'position',[150,28,180,52])

add_block('built-in/Transport Delay',[sys,'/','JK flip-flop/Transport Delay1'])
set_param([sys,'/','JK flip-flop/Transport Delay1'],...
		'Initial Input','1',...
		'position',[80,25,130,55])


%     Subsystem  'JK flip-flop/AND'.

new_system([sys,'/','JK flip-flop/AND'])
set_param([sys,'/','JK flip-flop/AND'],'Location',[59,237,323,377])

add_block('built-in/Inport',[sys,'/','JK flip-flop/AND/in_2'])
set_param([sys,'/','JK flip-flop/AND/in_2'],...
		'Port','2',...
		'position',[15,70,35,90])

add_block('built-in/Inport',[sys,'/','JK flip-flop/AND/in_1'])
set_param([sys,'/','JK flip-flop/AND/in_1'],...
		'position',[15,55,35,75])

add_block('built-in/Mux',[sys,'/','JK flip-flop/AND/Mux'])
set_param([sys,'/','JK flip-flop/AND/Mux'],...
		'inputs','2',...
		'position',[65,55,95,90])

add_block('built-in/Combinatorial Logic',[sys,'/','JK flip-flop/AND/AND'])
set_param([sys,'/','JK flip-flop/AND/AND'],...
		'Truth Table','[0;0;0;1]',...
		'position',[130,55,185,95])

add_block('built-in/Outport',[sys,'/','JK flip-flop/AND/out_1'])
set_param([sys,'/','JK flip-flop/AND/out_1'],...
		'position',[215,65,235,85])
add_line([sys,'/','JK flip-flop/AND'],[190,75;210,75])
add_line([sys,'/','JK flip-flop/AND'],[40,80;60,80])
add_line([sys,'/','JK flip-flop/AND'],[40,65;60,65])
add_line([sys,'/','JK flip-flop/AND'],[100,75;125,75])
set_param([sys,'/','JK flip-flop/AND'],...
		'Mask Display','AND',...
		'Mask Type','AND',...
		'Mask Dialogue','AND Gate',...
		'Mask Help','Calculates the logical AND of the two inputs.')


%     Finished composite block 'JK flip-flop/AND'.

set_param([sys,'/','JK flip-flop/AND'],...
		'position',[215,34,250,61])

add_block('built-in/Transport Delay',[sys,'/','JK flip-flop/Transport Delay2'])
set_param([sys,'/','JK flip-flop/Transport Delay2'],...
		'orientation',2,...
		'Initial Input','ini',...
		'position',[385,155,435,185])

add_block('built-in/Fcn',[sys,'/','JK flip-flop/Fcn'])
set_param([sys,'/','JK flip-flop/Fcn'],...
		'orientation',2,...
		'Expr','u[1]>.2',...
		'position',[305,158,350,182])

add_block('built-in/Inport',[sys,'/','JK flip-flop/in_3'])
set_param([sys,'/','JK flip-flop/in_3'],...
		'Port','3',...
		'position',[75,105,95,125])

add_block('built-in/Inport',[sys,'/','JK flip-flop/in_2'])
set_param([sys,'/','JK flip-flop/in_2'],...
		'position',[50,95,70,115])

add_block('built-in/Inport',[sys,'/','JK flip-flop/in_1'])
set_param([sys,'/','JK flip-flop/in_1'],...
		'Port','2',...
		'position',[15,75,35,95])

add_block('built-in/Mux',[sys,'/','JK flip-flop/Mux'])
set_param([sys,'/','JK flip-flop/Mux'],...
		'position',[300,87,330,133])

add_block('built-in/Combinatorial Logic',[sys,'/','JK flip-flop/Logic'])
set_param([sys,'/','JK flip-flop/Logic'],...
		'Truth Table','[0 1;1 0;0 1;1 0;0 1;1 0;0 1;1 0;0 1;1 0;0 1;0 1;1 0;1 0;1 0;0 1]',...
		'position',[360,90,415,130])

add_block('built-in/Demux',[sys,'/','JK flip-flop/Demux'])
set_param([sys,'/','JK flip-flop/Demux'],...
		'outputs','2',...
		'position',[435,90,475,125])

add_block('built-in/Outport',[sys,'/','JK flip-flop/out_2'])
set_param([sys,'/','JK flip-flop/out_2'],...
		'Port','2',...
		'position',[520,105,540,125])

add_block('built-in/Outport',[sys,'/','JK flip-flop/out_1'])
set_param([sys,'/','JK flip-flop/out_1'],...
		'position',[550,90,570,110])
add_line([sys,'/','JK flip-flop'],[185,40;210,40])
add_line([sys,'/','JK flip-flop'],[135,40;145,40])
add_line([sys,'/','JK flip-flop'],[300,170;265,170;265,125;295,125])
add_line([sys,'/','JK flip-flop'],[380,170;355,170])
add_line([sys,'/','JK flip-flop'],[480,100;480,170;440,170])
add_line([sys,'/','JK flip-flop'],[255,50;260,50;260,95;295,95])
add_line([sys,'/','JK flip-flop'],[40,85;200,85;210,55])
add_line([sys,'/','JK flip-flop'],[40,85;45,85;45,40;75,40])
add_line([sys,'/','JK flip-flop'],[75,105;295,105])
add_line([sys,'/','JK flip-flop'],[100,115;295,115])
add_line([sys,'/','JK flip-flop'],[480,115;515,115])
add_line([sys,'/','JK flip-flop'],[480,100;545,100])
add_line([sys,'/','JK flip-flop'],[420,110;430,110])
add_line([sys,'/','JK flip-flop'],[335,110;355,110])
set_param([sys,'/','JK flip-flop'],...
		'Mask Display','J    1\n\n>        \n\nK    0',...
		'Mask Type','JK flip-flop',...
		'Mask Dialogue','JK flip-flop|Initial State for Output "1":',...
		'Mask Translate','ini=(@1~=0);')
set_param([sys,'/','JK flip-flop'],...
		'Mask Help','When the clock signal is high, if the uncomp- lemented output is currently zero and J becomes one, the output will change to one.  K has no effect on the output in this case.  If the current value of the uncomplemented output is one and K becomes one, the output will change to zero.  J will have no effect on the output in this case.  The system clock period is used to set the state feedback delay of the flip-flop.')
set_param([sys,'/','JK flip-flop'],...
		'Mask Entries','0\/')


%     Finished composite block 'JK flip-flop'.

set_param([sys,'/','JK flip-flop'],...
		'position',[165,112,210,188])


%     Subsystem  'SR flip-flop'.

new_system([sys,'/','SR flip-flop'])
set_param([sys,'/','SR flip-flop'],'Location',[136,202,614,399])

add_block('built-in/Transport Delay',[sys,'/','SR flip-flop/Transport Delay1'])
set_param([sys,'/','SR flip-flop/Transport Delay1'],...
		'Initial Input','1',...
		'position',[100,10,150,40])


%     Subsystem  'SR flip-flop/AND'.

new_system([sys,'/','SR flip-flop/AND'])
set_param([sys,'/','SR flip-flop/AND'],'Location',[59,237,323,377])

add_block('built-in/Outport',[sys,'/','SR flip-flop/AND/out_1'])
set_param([sys,'/','SR flip-flop/AND/out_1'],...
		'position',[215,65,235,85])

add_block('built-in/Combinatorial Logic',[sys,'/','SR flip-flop/AND/AND'])
set_param([sys,'/','SR flip-flop/AND/AND'],...
		'Truth Table','[0;0;0;1]',...
		'position',[130,55,185,95])

add_block('built-in/Mux',[sys,'/','SR flip-flop/AND/Mux'])
set_param([sys,'/','SR flip-flop/AND/Mux'],...
		'inputs','2',...
		'position',[65,55,95,90])

add_block('built-in/Inport',[sys,'/','SR flip-flop/AND/in_1'])
set_param([sys,'/','SR flip-flop/AND/in_1'],...
		'position',[15,55,35,75])

add_block('built-in/Inport',[sys,'/','SR flip-flop/AND/in_2'])
set_param([sys,'/','SR flip-flop/AND/in_2'],...
		'Port','2',...
		'position',[15,70,35,90])
add_line([sys,'/','SR flip-flop/AND'],[100,75;125,75])
add_line([sys,'/','SR flip-flop/AND'],[40,65;60,65])
add_line([sys,'/','SR flip-flop/AND'],[40,80;60,80])
add_line([sys,'/','SR flip-flop/AND'],[190,75;210,75])
set_param([sys,'/','SR flip-flop/AND'],...
		'Mask Display','AND',...
		'Mask Type','AND',...
		'Mask Dialogue','AND Gate',...
		'Mask Help','Calculates the logical AND of the two inputs.')


%     Finished composite block 'SR flip-flop/AND'.

set_param([sys,'/','SR flip-flop/AND'],...
		'position',[235,19,270,46])

add_block('built-in/Inport',[sys,'/','SR flip-flop/in_1'])
set_param([sys,'/','SR flip-flop/in_1'],...
		'Port','2',...
		'position',[45,40,65,60])

add_block('built-in/Fcn',[sys,'/','SR flip-flop/Fcn1'])
set_param([sys,'/','SR flip-flop/Fcn1'],...
		'Expr','u[1]<.2',...
		'position',[170,13,200,37])

add_block('built-in/Fcn',[sys,'/','SR flip-flop/Fcn'])
set_param([sys,'/','SR flip-flop/Fcn'],...
		'orientation',2,...
		'Expr','u[1]>.2',...
		'position',[190,148,225,172])

add_block('built-in/Transport Delay',[sys,'/','SR flip-flop/Transport Delay'])
set_param([sys,'/','SR flip-flop/Transport Delay'],...
		'orientation',2,...
		'Initial Input','ini',...
		'position',[270,145,315,175])

add_block('built-in/Combinatorial Logic',[sys,'/','SR flip-flop/Logic'])
set_param([sys,'/','SR flip-flop/Logic'],...
		'Truth Table','[0 1;1 0;0 1;1 0;0 1;1 0;0 1;1 0;0 1;1 0;0 1;0 1;1 0;1 0;0 0;0 0]',...
		'position',[220,80,275,120])

add_block('built-in/Mux',[sys,'/','SR flip-flop/Mux'])
set_param([sys,'/','SR flip-flop/Mux'],...
		'position',[170,77,200,123])

add_block('built-in/Demux',[sys,'/','SR flip-flop/Demux'])
set_param([sys,'/','SR flip-flop/Demux'],...
		'outputs','2',...
		'position',[300,80,340,115])

add_block('built-in/Outport',[sys,'/','SR flip-flop/out_1'])
set_param([sys,'/','SR flip-flop/out_1'],...
		'position',[385,80,405,100])

add_block('built-in/Inport',[sys,'/','SR flip-flop/in_3'])
set_param([sys,'/','SR flip-flop/in_3'],...
		'Port','3',...
		'position',[120,95,140,115])

add_block('built-in/Inport',[sys,'/','SR flip-flop/in_2'])
set_param([sys,'/','SR flip-flop/in_2'],...
		'position',[85,85,105,105])

add_block('built-in/Outport',[sys,'/','SR flip-flop/out_2'])
set_param([sys,'/','SR flip-flop/out_2'],...
		'Port','2',...
		'position',[410,95,430,115])
add_line([sys,'/','SR flip-flop'],[145,105;165,105])
add_line([sys,'/','SR flip-flop'],[110,95;165,95])
add_line([sys,'/','SR flip-flop'],[205,100;215,100])
add_line([sys,'/','SR flip-flop'],[280,100;295,100])
add_line([sys,'/','SR flip-flop'],[345,105;405,105])
add_line([sys,'/','SR flip-flop'],[345,90;360,90;360,160;320,160])
add_line([sys,'/','SR flip-flop'],[360,90;380,90])
add_line([sys,'/','SR flip-flop'],[155,25;165,25])
add_line([sys,'/','SR flip-flop'],[205,25;230,25])
add_line([sys,'/','SR flip-flop'],[275,35;290,35;290,60;160,60;165,85])
add_line([sys,'/','SR flip-flop'],[70,50;215,50;215,40;230,40])
add_line([sys,'/','SR flip-flop'],[70,50;80,50;80,25;95,25])
add_line([sys,'/','SR flip-flop'],[265,160;230,160])
add_line([sys,'/','SR flip-flop'],[185,160;160,160;165,115])
set_param([sys,'/','SR flip-flop'],...
		'Mask Display','S    1\n\n>        \n\nR    0',...
		'Mask Type','SR flip-flop',...
		'Mask Dialogue','SR flip-flop|Initial State for Output "1":',...
		'Mask Translate','ini=(@1~=0);')
set_param([sys,'/','SR flip-flop'],...
		'Mask Help','When the clock signal is high, if S is one, the uncomplemented output will change to one.  If R is one, the uncomplemented output will become zero.  If both S and R are one, the output will be in an undefined state.')
set_param([sys,'/','SR flip-flop'],...
		'Mask Entries','0\/')


%     Finished composite block 'SR flip-flop'.

set_param([sys,'/','SR flip-flop'],...
		'position',[45,112,90,188])


%     Subsystem  'Latch'.

new_system([sys,'/','Latch'])
set_param([sys,'/','Latch'],'Location',[102,336,551,502])

add_block('built-in/Inport',[sys,'/','Latch/in_2'])
set_param([sys,'/','Latch/in_2'],...
		'Port','2',...
		'position',[50,65,70,85])

add_block('built-in/Inport',[sys,'/','Latch/in_1'])
set_param([sys,'/','Latch/in_1'],...
		'position',[20,50,40,70])

add_block('built-in/Mux',[sys,'/','Latch/Mux'])
set_param([sys,'/','Latch/Mux'],...
		'inputs','3',...
		'position',[135,59,165,91])

add_block('built-in/Outport',[sys,'/','Latch/out_1'])
set_param([sys,'/','Latch/out_1'],...
		'position',[355,55,375,75])

add_block('built-in/Outport',[sys,'/','Latch/out_2'])
set_param([sys,'/','Latch/out_2'],...
		'Port','2',...
		'position',[395,70,415,90])

add_block('built-in/Transport Delay',[sys,'/','Latch/Transport Delay'])
set_param([sys,'/','Latch/Transport Delay'],...
		'orientation',2,...
		'Initial Input','ini',...
		'position',[250,120,295,150])

add_block('built-in/Combinatorial Logic',[sys,'/','Latch/Logic'])
set_param([sys,'/','Latch/Logic'],...
		'Truth Table','[0 1;1 0;0 1;0 1;1 0;1 0;0 0;0 0]',...
		'position',[195,55,250,95])

add_block('built-in/Demux',[sys,'/','Latch/Demux'])
set_param([sys,'/','Latch/Demux'],...
		'outputs','2',...
		'position',[275,55,315,90])

add_block('built-in/Fcn',[sys,'/','Latch/Fcn'])
set_param([sys,'/','Latch/Fcn'],...
		'orientation',2,...
		'Expr','u[1]>.2',...
		'position',[170,123,205,147])
add_line([sys,'/','Latch'],[320,80;390,80])
add_line([sys,'/','Latch'],[255,75;270,75])
add_line([sys,'/','Latch'],[170,75;190,75])
add_line([sys,'/','Latch'],[45,60;105,60;105,65;130,65])
add_line([sys,'/','Latch'],[75,75;130,75])
add_line([sys,'/','Latch'],[245,135;210,135])
add_line([sys,'/','Latch'],[165,135;110,135;110,85;130,85])
add_line([sys,'/','Latch'],[320,65;350,65])
add_line([sys,'/','Latch'],[335,65;335,135;300,135])
set_param([sys,'/','Latch'],...
		'Mask Display','S  1\n\nR  0',...
		'Mask Type','Latch',...
		'Mask Dialogue','Latch|Initial State for Output "1":',...
		'Mask Translate','ini=(@1~=0);')
set_param([sys,'/','Latch'],...
		'Mask Help','Latches the S input.  When S (set) is one, the uncomplemented output (1) becomes one.  The output remains one until the R (reset) input becomes one, forcing the output to zero.  If both R and S are one, the latch will be in an undefined state.')
set_param([sys,'/','Latch'],...
		'Mask Entries','0\/')


%     Finished composite block 'Latch'.

set_param([sys,'/','Latch'],...
		'position',[50,32,85,83])

add_block('built-in/Note',[sys,'/',['NOTE:',13,'The flip-flop blocks are triggered by the',13,'rising edge of a clock signal.  The above ',13,'clock block is specifically designed to   ',13,'provide a sharp rising and falling edge   ',13,'for use with these flip-flops. Other input ',13,'signals may result in error. ']])
set_param([sys,'/',['NOTE:',13,'The flip-flop blocks are triggered by the',13,'rising edge of a clock signal.  The above ',13,'clock block is specifically designed to   ',13,'provide a sharp rising and falling edge   ',13,'for use with these flip-flops. Other input ',13,'signals may result in error. ']],...
		'position',[140,285,145,290])


%     Subsystem  'Clock'.

new_system([sys,'/','Clock'])
set_param([sys,'/','Clock'],'Location',[471,305,788,438])

add_block('built-in/Sum',[sys,'/','Clock/Sum'])
set_param([sys,'/','Clock/Sum'],...
		'inputs','+-',...
		'position',[115,30,135,50])

add_block('built-in/Unit Delay',[sys,'/','Clock/Unit Delay'])
set_param([sys,'/','Clock/Unit Delay'],...
		'orientation',2,...
		'Sample time','duration',...
		'position',[125,80,175,100])

add_block('built-in/Outport',[sys,'/','Clock/out_1'])
set_param([sys,'/','Clock/out_1'],...
		'position',[240,30,260,50])

add_block('built-in/Constant',[sys,'/','Clock/Constant'])
set_param([sys,'/','Clock/Constant'],...
		'position',[25,25,45,45])

add_block('built-in/Discrete Transfer Fcn',[sys,'/','Clock/Dis. Transfer Fcn'])
set_param([sys,'/','Clock/Dis. Transfer Fcn'],...
		'Denominator','[1 ]',...
		'Sample time','[duration, duration/20]',...
		'position',[210,202,255,238])

add_block('built-in/Discrete Transfer Fcn',[sys,'/','Clock/Dis. Transfer Fcn1'])
set_param([sys,'/','Clock/Dis. Transfer Fcn1'],...
		'Denominator','[1 ]',...
		'Sample time','[duration, duration-duration/20]',...
		'position',[90,202,135,238])
add_line([sys,'/','Clock'],[50,35;110,35])
add_line([sys,'/','Clock'],[140,40;210,40;210,90;180,90])
add_line([sys,'/','Clock'],[120,90;85,90;85,45;110,45])
add_line([sys,'/','Clock'],[140,40;235,40])
set_param([sys,'/','Clock'],...
		'Mask Display','plot(0,0,100,100,[90,75,75,60,60,35,35,20,20,10],[20,20,80,80,19,20,80,80,20,20])',...
		'Mask Type','Digital clock')
set_param([sys,'/','Clock'],...
		'Mask Dialogue','Digital clock.\nOutput is set to 1 for the first half of the period.|Period:',...
		'Mask Translate','duration = @1/2;',...
		'Mask Help','Digital clock for logic systems.')
set_param([sys,'/','Clock'],...
		'Mask Entries','2\/')


%     Finished composite block 'Clock'.

set_param([sys,'/','Clock'],...
		'position',[50,231,90,259])


%     Subsystem  'Demo'.

new_system([sys,'/','Demo'])
set_param([sys,'/','Demo'],'Location',[60,206,282,425])
set_param([sys,'/','Demo'],...
		'Mask Display','DEMO',...
		'Mask Dialogue','eval(''logdemo'');')


%     Finished composite block 'Demo'.

set_param([sys,'/','Demo'],...
		'hide name',0,...
		'position',[162,229,209,261])

add_block('built-in/Note',[sys,'/','Flip-flops'])
set_param([sys,'/','Flip-flops'],...
		'position',[125,5,130,10])

drawnow

% Return any arguments.
if (nargin | nargout)
	% Must use feval here to access system in memory
	if (nargin > 3)
		if (flag == 0)
			eval(['[ret,x0,str,ts,xts]=',sys,'(t,x,u,flag);'])
		else
			eval(['ret =', sys,'(t,x,u,flag);'])
		end
	else
		[ret,x0,str,ts,xts] = feval(sys);
	end
else
	drawnow % Flash up the model and execute load callback
end
