
/*                                                                  */
/*  THE QUICK SIMULATOR BENCHMARK - BY DAVID GREER, AS DESCRIBED    */
/*  IN "VLSI SYSTEMS DESIGN", NOVEMBER, 1987.                       */
/*                                                                  */
/*  VERILOG DESCRIPTION BY STU SUTHERLAND.                          */
/*                                                                  */
/*  IN MODULE "TOP", UNCOMMENT THE APPROPRIATE LINE TO SELECT AN    */
/*  INSTANCE OF THE DESIRED CIRCUIT SIZE.                           */
/*                                                                  */
/*  IN THE MODULE "lfsr100", UNCOMMENT THE APPROPRIATE LINE TO USE  */
/*  USE EITHER A 10 GATE FLIP FLOP MODEL OR A 1 GATE USER-DEFINED-  */
/*  PRIMITIVE FLIP FLOP MODEL.                                      */
/*                                                                  */
/*  BE SURE TO UNCOMMENT ALL MODULES REFERENCED BY THE CIRCUIT      */
/*  SIZE SELECTED (AND COMMENT OUT ANY UNUSED MODULES TO CONSERVE   */
/*  SYSTEM MEMORY USAGE).                                           */
/*                                                                  */
/*  SYSTEM MEMORY REQUIREMENTS (APPROXIMATES):                      */
/*                                                                  */
/*                            10-GATE-FLIP-FLOP     UDP-FLIP-FLOP   */
/*        CIRCUIT SIZE        COMPILE  SIMULATE   COMPILE  SIMULATE */
/*                                                                  */
/*   10K GATES (  1K FLOPS)     5 meg    3 meg      1 meg    1 meg  */
/*   50K GATES (  5K FLOPS)    18 meg    8 meg      4 meg    2 meg  */
/*  100K GATES ( 10K FLOPS)    36 meg   16 meg      7 meg    4 meg  */
/*  200K GATES ( 20K FLOPS)    66 meg   32 meg     14 meg    6 meg  */
/*  500K GATES ( 50K FLOPS)   158 meg   64 meg     30 meg   12 meg  */
/*  1meg GATES (100K FLOPS)   300 meg  128 meg     60 meg   24 meg  */
/*                                                                  */
/********************************************************************/

`accelerate                            //use the XL (-a) option

module TOP;
  `define period 10
  `define cycles 10000
  reg reset;  
  nand #(`period/2) (clk,clk,reset);   //clock oscillator
    lfsr5k   lfsr (a, a, clk, reset);
//  lfsr10k  lfsr (a, a, clk, reset);
//  lfsr50k  lfsr (a, a, clk, reset);
//  lfsr100k lfsr (a, a, clk, reset);
//  lfsr200k lfsr (a, a, clk, reset);
//  lfsr500k lfsr (a, a, clk, reset);
//  lfsr1meg lfsr (a, a, clk, reset);
  initial
    begin
	$dumpvars;
    $utConnectivity;
    $utLimitVCD(1);
    $stop;
//      lib.begin_stats;
//    $showallinstances;
      reset = 0;
      #`period reset = 1;
      #(`period * `cycles);
//      lib.end_stats;
      $finish(2);
    end
//  always @clk $display($stime,"  clk = %b  lfsr_out = %b",clk,a);
endmodule
/*********************************************************************/
macromodule dflop_gate (q, d, clk, rst);    //dflop (10 gates)
  output  q;
  input   d, clk, rst;
  not  #1 (clk_, clk);
  not  #1 (d_, d);
  nand #1 (n2, d_, clk_);
  nand #1 (n3, n1, n4);
  nand #1 (q, n5, q_);
  nand #1 (n1, d, clk_, rst);
  nand #1 (n4, n2, n3, rst);
  nand #1 (n5, n3, clk);
  nand #1 (n6, n4, clk);
  nand #1 (q_, n6, rst, q);
endmodule
/*********************************************************************/
/*
primitive dflop_udp (q, d, clk, rst);  //dflop (1 primitive)
  output q;
  input  d, clk, rst;
  reg    q;
  table
  // d  clk  rst  state  q
     ?   ?    0  :  ?  : 0 ;  //reset active lo
     ?   ?    *  :  ?  : - ;
     0  (01)  1  :  ?  : 0 ;  //positive edge triggered
     1  (01)  1  :  ?  : 1 ;
     0  (0?)  1  :  0  : - ;  //reduce pessimism
     1  (0?)  1  :  1  : - ;
     ?  (?0)  1  :  ?  : - ;
     *   ?    1  :  ?  : - ;
  endtable
endprimitive
*/
/*********************************************************************/
module lfsr100 (b1, a1, clk, reset);   //10 dflops (100 gates)
  output b1;                           
  input  a1, clk, reset;
  xnor   (x1, a1, q7);                 //feedback loop
//  dflop_udp  d1  (q1, x1, clk, reset), //use UDP Flip Flop
    dflop_gate d1  (q1, x1, clk, reset), //use 10-gate Flip Flop
             d2  (q2, q1, clk, reset),
             d3  (q3, q2, clk, reset),
             d4  (q4, q3, clk, reset),
             d5  (q5, q4, clk, reset),
             d6  (q6, q5, clk, reset),
             d7  (q7, q6, clk, reset),
             d8  (q8, q7, clk, reset),
             d9  (q9, q8, clk, reset),
             d10 (b1, q9, clk, reset);
endmodule
/*********************************************************************/
module lfsr1k (b2, a2, clk, reset);    //100 dflops (1,000 gates)
  output  b2;
  input   a2, clk, reset;
  lfsr100 l1  (q1, a2, clk, reset),
          l2  (q2, q1, clk, reset),
          l3  (q3, q2, clk, reset),
          l4  (q4, q3, clk, reset),
          l5  (q5, q4, clk, reset),
          l6  (q6, q5, clk, reset),
          l7  (q7, q6, clk, reset),
          l8  (q8, q7, clk, reset),
          l9  (q9, q8, clk, reset),
          l10 (b2, q9, clk, reset); 
endmodule  
/*********************************************************************/
/*
module lfsr10k (b3, a3, clk, reset);   //1,000 dflops (10,000 gates)
  output b3;
  input  a3, clk, reset;
  lfsr1k l1  (q1, a3, clk, reset),
         l2  (q2, q1, clk, reset),
         l3  (q3, q2, clk, reset),
         l4  (q4, q3, clk, reset),
         l5  (q5, q4, clk, reset),
         l6  (q6, q5, clk, reset),
         l7  (q7, q6, clk, reset),
         l8  (q8, q7, clk, reset),
         l9  (q9, q8, clk, reset),
         l10 (b3, q9, clk, reset); 
endmodule  
*/
/*********************************************************************/
module lfsr5k (b3, a3, clk, reset);   //500 dflops (5,000 gates)
  output b3;
  input  a3, clk, reset;
  lfsr1k l1  (q1, a3, clk, reset),
         l2  (q2, q1, clk, reset),
         l3  (q3, q2, clk, reset),
         l4  (q4, q3, clk, reset),
         l5  (b3, q4, clk, reset);
endmodule  
