
This directory contains of 9 files.

(1) A README file that contains instructions on how to use the analyzer 
    and a description of the contents of all the files.
(2) The Verilog analyzer itself (finva).
(3) A key file called fintronc.key which is empty. User should contact 
    Fintronic USA and provide a hostid and hostname to get a valid key file.
(4) A Verilog example that fails in the first phase of analysis (bad1.v).
(5) A Verilog example that fails in the second phase of analysis (bad2.v).
(6) A Verilog example that fails in the third phase of analysis (bad3.v).
(7) A good Verilog example (good.v).
(8) The user's guide in latex (users_guide.tex).
(9) The user's guide in postscript (users_guide.ps).

In order to use the analyzer the user must set the environment variable 
FIN_LICENSE_PATH to the directory that contains the key file fintronc.key.
   e.g. setenv FIN_LICENSE_PATH /u1/fin_vlog

For large designs the -is option (described later) should be used.

The analyzer should be invoked as follows:

va <option or source file name> <option or source file name> ... 

The legal options are:
-cf <file>  : take command line information from the specified command file
-id <dir>   : search for include files in the specified include directory
-ld <dir>   : search for undeclared modules in the specified library directory
-lf <file>  : search for undeclared modules in the specified library file
-le <str>   : use the specified string as the file extension when searching for
              undeclared modules in library directories
-lsm <str>  : the specified string describes the library search mechanism to
              use, it must be one of d (default), o (order) or r (rescan)
-ustf       : suppress warning messages about unknown system tasks/functions
-ind        : suppress warning messages about implicit net declarations
-ubd        : suppress warning messages about objects used before they are
              declared
-ncd        : suppress warning messages about non constant delay expressions
-rd         : suppress warning messages about delay expressions of type real
-nd         : suppress warning messages about negative delay expressions
-xzd        : suppress warning messages about delay expressions that contain
              x's or z's
-tc         : suppress warning messages about type conversions performed on
              expression operands
-tmarg      : suppress warning messages about type mismatches between actual
              and formal arguments of tasks/functions
-wmarg      : suppress warning messages about width mismatches between actual
              and formal arguments of tasks/functions
-twmarg     : same as "-tmarg -wmarg"
-tmgate     : suppress warning messages about type mismatches between gate
              terminals and the expressions connected to them
-wmgate     : suppress warning messages about width mismatches between gate
              terminals and the expressions connected to them
-twmgate    : same as "-tmgate -wmgate"
-tmport     : suppress warning messages about type mismatches between
              module/primitive ports and the expressions connected to them
-wmport     : suppress warning messages about width mismatches between
              module/primitive ports and the expressions connected to them
-twmport    : same as "-tmport -wmport"
-tmass      : suppress warning messages about type mismatches between the lhs
              and rhs of assignments
-wmass      : suppress warning messages about width mismatches between the lhs
              and rhs of assignments
-twmass     : same as "-tmass -wmass"
-tmcel      : suppress warning messages about type mismatches between case
              expressions and case labels
-wmcel      : suppress warning messages about width mismatches between case
              expressions and case labels
-twmcel     : same as "-tmcel -wmcel"
-tm         : same as "-tmarg -tmgate -tmport -tmass -tmcel"
-wm         : same as "-wmarg -wmgate -wmport -wmass -wmcel"
-twm        : same as "-twmarg -twmgate -twmport -twmass -twmcel"
-a          : suppress all warning messages
-min        : use the min component in min:typ:max expressions for analysis
-typ        : use the typ component in min:typ:max expressions for analysis,
              this is also the default
-max        : use the max component in min:typ:max expressions for analysis
-des <str>  : use the specified string as the name of the design
-ao         : perform syntax and semantic analysis only, do not generate
              code and data for simulation
-stb        : print the symbol table (in file stb.out)
-vpp        : print the result of the preprocessor (in file vpp.out)
-ifb        : print the intermediate format in binary (in file ifb.out)
-ifa        : print the intermediate format in ascii (in file ifa.out)
-is n:a:c:s : n, a, c and s are positive integers indicating the initial sizes
              of the node, attribute, char and string arrays respectively.
              a, c and s are optional

*** IMPORTANT ***
The analyzer when invoked on a large design may generate messages of the form:
     "Expanding node space to <number>",
     "Expanding attribute space to <number>",
     "Expanding string space to <number>".
     "Expanding char space to <number>".
     "Expanding node space to <number>",
     "Expanding attribute space to <number>",
etc.

To make the analyzer run much faster on these designs the user should
invoke the analyzer as follows va -is <max_nodes>:<max_attributes>:<max_chars>:<max_strings>.

For simplicity one may just always invoke it with a large number e.g.
alias va "va -is 1500000:1500000:500000:125000"

There are many classes of WARNING messages some of them can be suppressed
individually as mentioned above (and some can't). A future release will enable
users to supress each class of warning message individually.

A large number of warning messages may be generated for some designs
Invoking va with the options -us -ind -ubd -rd -tc -twmarg -twmass
may be serve as a good filter.

PLEASE READ THE USER'S GUIDE FOR DETAILS


Contacting Fintronic for license and information
================================================

You can request license to run FinSim Verilog Analyzer by sending us
the hostname and the hostid of your machine by either phone, fax or
E-mail.

Fintronic USA, Inc.
1360 Willow Rd, Ste 205
Menlo Park, CA 94025

Tel: +1.415.325.4474
Fax: +1.415.325.4908
Internet: info@fintronic.com


We welcome all your inquiries.